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The Research on Low-energy Test for SoC and BIST Which Based on the State Seeds

低功耗SoC测试技术及基于状态种子的BIST策略研究

In this page a BIST test vector generator used for IDDT test is designed .

本文设计了一种用于瞬态电流测试的BIST测试向量生成器。

This BIST structure has a little influence on the inner multiplier structure and its speed .

所实现的测试结构对乘法器的内部结构和运算速度影响很小，而且测试结构所占的比例也很小.

Work focuses on test algorithm , design , usage and BIST based on BST.

重点对基于边界扫描的测试算法、设计、应用和基于其上的BIST设计进行了研究。

A BIST test scheme of embedded DRAM The Graphic User Interface for Embedded System

嵌入式DRAM的BIST测试方法的研究嵌入式的图形用户界面